Axon
Zero-Copy High-Performance
Host–Network Interface Architecture
for Gigabit Communication

Axon is a zero-copy gigabit bandwidth host–network interface architecture that was designed and extensively simulated at Washington University in St. Louis from 1988 through 1992, encompassing host and network interface architecture, operating systems, and protocols.

We believe Axon to be the first zero-copy host network interface, one of the first two hardware hardware integration of protocol layers, and the first application of distributed virtual shared memory over a wide area network.

The technical reports are the earliest reports of the work and are generally more detailed versions of the published papers. All of them are in the original PostScript generated from from LaTeX/TeX. Unfortunately, conversion to PDF seems non-trivial, but eventually I hope to do this. If you are unfortunate enough to be on a MS-Windows box, you should get Ghostscript and GSview to allow easy viewing and printing of PostScript files (even if you have full Adobe Acrobat). Both are needed and installation is easy; the download pages are:

Axon Architecture

James P.G. Sterbenz and Gurudatta M. Parulkar,
Axon: A High-Speed Communication Architecture for Distributed Applications,
Washington University Department of Computer Science,
technical report WUCS-89-36, 7 September 1989,
presented at the Fourth IEEE ComSoc Workshop on Computer Communications,
Dana Point, California, Oct-Nov 1989.
[ PostScript ]

James P.G. Sterbenz and Gurudatta M. Parulkar,
“Axon: A High-Speed Communication Architecture for Distributed Applications“,
Proceedings of the Ninth Annual Joint Conference of the IEEE Computer and Communications Societies (INFOCOM'90),
Vol.II, IEEE Computer Society, Washington D.C., June 1990, pp. 415–425.
[ abstract | PostScript ]

Distributed Virtual Shared Memory

The Multics operating system provides an elegant memory model that is naturally extensible to reference objects throughout the network. We used this as a basis to allow programs to translucently access data throughout the network (if a program wants to determine whether a segment object is local or remote it can).

Packets are first class objects in the [segment, page, packet] virtual memory structure, thus providing the self describing and mapping mechanisms to allow zero-copy transfer for both transmit and receive. Packet sequence need not be preserved; we call this sequence by placement; the hardware simply marks the arrival of individual packets within a page in a bit vector, all bits set trigger page presence to the operating system.

James P.G. Sterbenz and Gurudatta M. Parulkar,
Axon: Network Virtual Storage Design,
Washington University Department of Computer Science,
technical report WUCS-89-13, 15 May 1989.
[ PostScript ]

James P.G. Sterbenz and Gurudatta M. Parulkar,
“Axon: Network Virtual Storage Design”,
SIGCOMM Computer Communication Review, Vol.20 #2,
ACM SIGCOMM, New York, April 1990, pp. 50–65.
[ abstract | PostScript ]

James P.G. Sterbenz and Gurudatta M. Parulkar,
“Axon: Network Virtual Storage for High Performance Distributed Applications”,
Proceedings of the Tenth IEEE International Conference on Distributed Computing Systems (ICDCS 10),
IEEE, Washington, D.C., May 1990, pp. 484–492.
[ abstract | PostScript ]

Application-Oriented Lightweight Transport Protocol

The ALTP-OT transport protocol was a necessary pice of the overall puzzle, but not a primary goal of this work. We simply designed a convienient transport protocol that allowed us to have self-describing packets for the zero-copy interface, supported the hardware-based error and flow control mechanisms, and transported objects at the granularity of segments (or segment groups for prefetching).

Anil Bhatia, James P.G. Sterbenz and Gurudatta M. Parulkar,
Comments on Proposed Transport Protocols,
Washington University Department of Computer Science,
technical report WUCS-88-30, October 1988.
[not available online]

James P.G. Sterbenz and Gurudatta M. Parulkar,
Axon: Application-Oriented Lightweight Transport Protocol Design,
Washington University Department of Computer Science,
technical report WUCS-89-14, 15 September 1989.
[ PostScript ]

James P.G. Sterbenz and Gurudatta M. Parulkar,
“Axon: Application-Oriented Lightweight Transport Protocol Design”,
Tenth International Conference on Computer Communication (ICCC'90),
ICCC, Narosa Publishing House, New Delhi, India, Nov. 1990, pp. 379–387.
[ abstract | PostScript ]

Zero-Copy Host-Network Interface Architecture and Design

The Axon host architecture consists of two major components:

  1. Eliminating I/O bottlenecks in the host by providing a direct path between the host memory and network interface independent of the I/O subsystem. The interface can either be through a richer processor–memory interconnect in which the network interface processor is simply treated as another processor with access to memory, or via the back-end sequential port of VRAM-style multiported memory.
  2. Pipelined zero-copy network interface that moves packets at line speed directly into host memory (or graphics frame buffer) by memory remapping; each packet has a descriptor that indicates its index into a virtual memory page.

James P.G. Sterbenz,
Axon: Host-Network Interface Design,
Washington University Department of Computer Science,
technical report WUCS-90-7, 31 March 1990.
[ PostScript ]

James P.G. Sterbenz and Gurudatta M. Parulkar,
“Axon Host-Network Interface Architecture for Gigabit Communications”,
Protocols for High Speed Networks II,
Marjory J. Johnson ed., IFIP WG6.1/6.4, Elsevier (North-Holland), 1991, pp. 211-236
[ abstract | PostScript online format ]

James P.G. Sterbenz, Anshul Kantawala, Millind M. Buddhikot, and Gurudatta M. Parulkar,
“Hardware Based Error and Flow Control in the Axon Gigabit Host–Network Interface”,
Proceedings of the Eleventh Annual Joint Conference of the IEEE Computer and Communications Societies (INFOCOM'92),
IEEE Computer Society, Washington D.C., 1992, pp. 282–293.
[ abstract | PostScript online format missing the lines referred to in the second line of column 2 on page 9 ]

James P.G. Sterbenz and Gurudatta M. Parulkar,
“Design of a Gigabit Host–-Network Interface”,
Journal of High Speed Networking, Vol.2 #1,
IOS Press, Amsterdam, 1993, pp. 27–62
[ abstract | PostScript online format missing the lines in Fig. 9 ]

Dissertation

Axon: A Host–Network Interface Architecture for Gigabit Communications,
D.Sc. in Computer Science,
Computer and Communications Research Center, Washington University in St. Louis, 1991.

The online version of this is under construction; the PostScript of chapters that still exist as single files are linked below. Eventually I hope to recreate the missing chapters.

  1. Motivation and Scope
  2. Network Virtual Storage
  3. Transport Protocol
  4. Host and Network Interface Architecture
  5. Simulation Model and Functional Verification
  6. Performance
  7. Conclusions
  8. Acknowledgments
  9. Appendix A: NVS Data Structures
  10. Appendix B: Block Diagram Catalog (removed from final printed version)

Dissertation Committee

Gurudatta M. Parulkar
advisor, g-troup leader, former director of the Washington University Applied Research Laboratory
David J. Farber
grand-advisor, f-troup leader
Jerome R. Cox, Jr.
chair of the Department of Computer Science when I was there
Gary Delp
f-troup member
Martin Dubetz
director of Academic Computing and Networking
Jon Turner
director of the Advanced Communications Systems group

Dissertation Proposal

James P.G. Sterbenz,
Host-Network Interface Architecture for Gigabit Communications,
D.Sc. dissertation proposal,
Washington University Department of Computer Science,
technical report WUCS-89-35, 25 August 1989.
[ PostScript ]

James P.G. Sterbenz,
High Performance Host and -Network Interface Architecture,
request for comments (first publicly circulated version of what would become WUCS-89-35),
December 1988.
[ not available online ]

Last updated 22 November 2003 – Valid XHTML 1.1 – Lynx inspected – W3C A Conformance
©2003 James P.G. Sterbenz <jpgs@sterbenz.org>